PIC18F442T-I/ML【PDF 96/134 页】IC MCU FLASH 8KX16 EE A/D 44QFN

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Sheet目录3882

92页 93页 94页 95页 [96页]97页 98页 99页 100页

PIC16C9XX

DS30444E - page 64

1997 Microchip Technology Inc.

FIGURE 11-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)

R/W-0

WCOL

SSPOV

SSPEN

CKP

SSPM3

SSPM2

SSPM1

SSPM0

R = Readable bit

W = Writable bit

U = Unimplemented bit,

read as ‘0’

- n =Value at POR reset

bit7

bit0

bit 7:

WCOL: Write Collision Detect bit

1 = The SSPBUF register is written while it is still transmitting the previous word

(must be cleared in software)

0 = No collision

bit 6:

SSPOV: Receive Overow Indicator bit

In SPI mode

1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overow,

the data in SSPSR is lost. Overow can only occur in slave mode. The user must read the SSPBUF, even

if only transmitting data, to avoid setting overow. In master mode the overow bit is not set since each

new reception (and transmission) is initiated by writing to the SSPBUF register.

0 = No overow

In I2C mode

1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don’t care"

in transmit mode. SSPOV must be cleared in software in either mode.

0 = No overow

bit 5:

SSPEN: Synchronous Serial Port Enable bit

In SPI mode

1 = Enables serial port and congures SCK, SDO, and SDI as serial port pins

0 = Disables serial port and congures these pins as I/O port pins

In I2C mode

1 = Enables the serial port and congures the SDA and SCL pins as serial port pins

0 = Disables serial port and congures these pins as I/O port pins

In both modes, when enabled, these pins must be properly congured as input or output.

bit 4:

CKP: Clock Polarity Select bit

In SPI mode

1 = Idle state for clock is a high level

0 = Idle state for clock is a low level

In I2C mode

SCK release control

1 = Enable clock

0 = Holds clock low (clock stretch) (Used to ensure data setup time)

bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits

0000

= SPI master mode, clock = FOSC/4

0001

= SPI master mode, clock = FOSC/16

0010

= SPI master mode, clock = FOSC/64

0011

= SPI master mode, clock = TMR2 output/2

0100

= SPI slave mode, clock = SCK pin. SS pin control enabled.

0101

= SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin

0110

= I2C slave mode, 7-bit address

0111

= I2C slave mode, 10-bit address

1011

= I2C Firmware controlled master mode (slave idle)

1110

= I2C slave mode, 7-bit address with start and stop bit interrupts enabled

1111

= I2C slave mode, 10-bit address with start and stop bit interrupts enabled

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